In response to an increased need for smaller electronic devices with higher circuit density, devices with three dimensional (3D) structures have been developed. An example of such device includes FinFET device having a conductive fin-like structure that are raised above the horizontally extending substrate. In conventional processing, a FinFET device substrate may comprise a semiconducting base, for example silicon (Si), and an oxide layer formed thereon. In other examples, a FinFET may be a silicon-on-insulator substrate. A conventional FinFET device includes a fin structure raised above the substrate and a gate structure that wraps around three sides of the fin structure along a portion of its length.
At various instances during fabrication of a FinFET device the fin structure may be subject to doping. For example dopants may be introduced into a region to form the channel of the field effect transistor being built in order to control threshold voltage. In fabrication of complementary metal oxide semiconductor (CMOS) devices using FinFET transistors, other implantation may be performed to generate n-wells or p-wells to isolated transistors of one dopant type from those of another dopant type. Additional implants that may reduce punch through such as halo, pocket or delta doping are also possible. In addition, when a gate structure is present, dopants can be introduced into the fin structure in regions that are not covered by the gate in order to form source/drain (S/D) regions or S/D extension regions.
One process that is used to dope the fin structure may be an ion implantation process. In this process, dopants having desired species may be directed toward the fin structure in a form of ions, and implanted therein. Although effective in doping, the ion implantation process is an energetic process which causes amorphization in the region within which the dopants are implanted. When used to implant dopants into the fin structure, the ion implantation process may cause the fin structure, which is otherwise mono-crystalline (single crystalline), to amorphize. Generally, the amorphization may be remedied with a post-implant process such as rapid thermal processing (RTP). As the width of the fin structure scales to 20 nm or less, however, excessive amorphization may be partially remedied with RTP or other post-implant processes. Even if remedied with the RTP process, the fin structure or portions of the fin structure may be in undesirable poly-crystalline state after RTP processing.
To avoid excessive amorphization of the fin structure, the implantation process in principle may be performed at a higher temperature, such as up to or greater than 500° C. The ion implantation at this temperature or above, however, precludes the use of photoresist, which is used to mask portions of the FinFET device that are not to be implanted during a given implantation process. As such new processes are needed to fabricate three dimensional devices such as FinFETs. It is with respect to these and other considerations that the present improvements have been needed.